DS90CR561_13 Datasheet, PDF (6/14 Pages) Texas Instruments – 18-Bit Color Flat Panel Display (FPD) Link

DS90CR561, DS90CR562
SNOS766B – JULY 1997 – REVISED APRIL 2013
OBSOLETE
AC Timing Diagrams
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Figure 6. “Worst Case” Test Pattern
The worst case test pattern produces a maximum toggling of device digital circuitry, LVDS I/O and TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 6 and Figure 7 show a rising edge data strobe (TxCLK IN/RxCLK OUT).
Recommended pin to signal mapping. Customer may choose to define differently.
Figure 7. “16 Grayscale” Test Pattern
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