DS90CR561_13 Datasheet, PDF (1/14 Pages) Texas Instruments – 18-Bit Color Flat Panel Display (FPD) Link

OBSOLETE
DS90CR561, DS90CR562
www.ti.com
SNOS766B – JULY 1997 – REVISED APRIL 2013
18-Bit Color Flat Panel Display (FPD) Link
Check for Samples: DS90CR561, DS90CR562
FEATURES
1
•2 Up to 105 Megabyte/sec bandwidth
• Narrow bus reduces cable size and cost
• 290 mV swing LVDS devices for low EMI
• Low power CMOS design
• Power-down mode
• PLL requires no external components
• Low profile 48-lead TSSOP package
• Rising edge data strobe
• Compatible with TIA/EIA-644 LVDS standard
DESCRIPTION
The DS90CR561 transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. The DS90CR562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 40 MHz, 18 bits
of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 280 Mbps per LVDS data channel. Using a
40 MHz clock, the data throughput is 105 Megabytes
per second. These devices are offered with rising
edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram
Figure 1. DS90CR561
See Package Number DGG
Figure 2. DS90CR562
See Package Number DGG
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated