DS90CR561_13 Datasheet, PDF (5/14 Pages) Texas Instruments – 18-Bit Color Flat Panel Display (FPD) Link

OBSOLETE
DS90CR561, DS90CR562
www.ti.com
SNOS766B – JULY 1997 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 22)
f = 40 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TCIP
TxCLK IN Period (Figure 12)
TCIH
TxCLK IN High Time (Figure 12)
TCIL
TxCLK IN Low Time (Figure 12)
TSTC TxIN Setup to TxCLK IN (Figure 12)
f = 20 MHz
f = 40 MHz
THTC TxIN Hold to TxCLK IN (Figure 12)
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay @ 25°C, V_CC = 5.0V (Figure 14)
Transmitter Phase Lock Loop Set (Figure 16)
TPDD Transmitter Powerdown Delay (Figure 20)
Min
−100
2.9
6.1
9.7
13
17
20.3
25
0.35T
0.35T
14
8
2.5
5
Typ
100
3.3
6.6
10.2
13.5
17.4
20.8
T
0.5T
0.5T
2
Max
300
3.9
7.1
10.7
14.1
17.8
21.4
50
0.65T
0.65T
9.7
10
100
Units
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 9)
3.5
6.5
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 9)
2.7
6.5
RCOP
RSKM
RxCLK OUT Period (Figure 13)
Receiver Skew Margin ⁽¹⁾V_CC = 5V, T_A = 25°C
(Figure 23)
f = 20 MHz
f = 40 MHz
25
T
50
1.1
700
RCOH
RxCLK OUT High Time (Figure 13)
f = 20 MHz
19
f = 40 MHz
6
RCOL
RxCLK OUT Low Time (Figure 13)
f = 20 MHz
21.5
f = 40 MHz
10.5
RSRC
RxCLK Setup to RxCLK OUT (Figure 13)
f = 20 MHz
14
f = 40 MHz
4.5
RHRC
RxCLK Hold to RxCLK OUT (Figure 13)
f = 20 MHz
16
f = 40 MHz
6
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 5.0V (Figure 15)
7.6
11.9
RPLLS
Receiver Phase Lock Loop Set (Figure 17)
10
RPDD
Receiver Powerdown Delay (Figure 21)
1
Units
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependant on the
type/length and source clock (TxCLK IN) jitter. RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
Copyright © 1997–2013, Texas Instruments Incorporated
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