CDC2586_08 Datasheet, PDF (6/14 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2586
SCAS337D – FEBRUARY 1993 – REVISED APRIL 2004
RECOMMENDED OPERATING CONDITIONS ⁽¹⁾
V_CC
Supply voltage
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_I
Input voltage
I_OH
High-level output current
I_OL
Low-level output current
T_A
Operating free-air temperature
(1) Unused inputs must be held high or low to prevent them from floating.
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MIN MAX UNIT
3
3.6 V
2
V
0.8 V
0
5.5 V
-12 mA
12 mA
0
70 °C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V_IK
V_OH
V_OL
I_I
I_OZH
I_OZL
I_CC
C_i
C_o
TEST CONDITIONS
V_CC = 3 V,
V_CC = MIN to MAX⁽¹⁾,
V_CC = 3 V,
V_CC = 3 V
V_CC = 0,
V_CC = 3.6 V,
V_CC = 3.6 V,
V_CC = 3.6 V,
V_CC = 3.6 V, I_O= 0,
V_I = V_CC or GND
V_I = V_CC or GND
V_O = V_CC or GND
I_I = -18 mA
I_OH = -100 µA
I_OH = -12 mA
I_OL = 100 µA
I_OL = 12 mA
V_I = 3.6 V
V_I = V_CC or GND
V_O = 3 V
V_O = 0
Outputs high
Outputs low
Outputs disabled
T_A = 25°C
MIN MAX
-1.2
V_CC-0.2
2
0.2
0.8
±10
±1
10
-10
1
1
1
4
8
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
UNIT
V
V
V
µA
µA
µA
mA
pF
pF
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
f_clock
Clock frequency
Input clock duty cycle
Stabilization time⁽¹⁾
VCO operating at four times the CLKIN frequency
VCO operating at double the CLKIN frequency
After SEL1, SEL0
After OE↓
After power up
After CLKIN
MIN
25
50
40%
MAX
50
100
60%
50
50
50
50
UNIT
MHz
µs
(1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to
be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristicstable are not applicable.
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