CD74HCT574-EP Datasheet, PDF (6/14 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOP 3-STATE,POSITIVE-EDGE TRIGGERED

CD74HCT574ĆEP
HIGHĆSPEED CMOS LOGIC OCTAL DĆTYPE FLIPĆFLOP
3ĆSTATE, POSITIVEĆEDGE TRIGGERED
SCLS571 − FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
RL = 1 kΩ ^S1
VCC
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Input
tw
1.3 V
3V
1.3 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Timing Input
1.3 V
0V
th
tsu
3V
Data Input
1.3 V
1.3 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.3 V
3V
1.3 V
0V
tPLH
In-Phase
Output
tPHL
1.3 V
tPHL
VOH
1.3 V
VOL
tPLH
Out-of-Phase
Output
1.3 V
1.3 V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
1.3 V
1.3 V
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
1.3 V
tPLZ
10%
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.3 V
tPHZ
90%
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3V
0V
≈VCC
VOL
VOH
≈0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
F. tPLH and tPHL are the same as tpd.
G. tPLZ and tPHZ are the same as tdis.
H. tPZH and tPZL are the same as ten.
Figure 1. Load Circuit and Voltage Waveforms
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