CD74HCT574-EP Datasheet, PDF (1/14 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOP 3-STATE,POSITIVE-EDGE TRIGGERED

CD74HCT574ĆEP
HIGHĆSPEED CMOS LOGIC OCTAL DĆTYPE FLIPĆFLOP
3ĆSTATE, POSITIVEĆEDGE TRIGGERED
SCLS571 − FEBRUARY 2004
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree^†
D Buffered Inputs
D Common 3-State Output-Enable Control
D 3-State Outputs
D Bus-Line Driving Capability
D Typical Propagation Delay (Clock to Q):
15 ns at V_CC = 5 V, C_L = 15 pF, T_A = 255C
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
D V_CC Voltage = 4.5 V to 5.5 V
D Direct LSTTL Input Logic Compatibility,
V_IL = 0.8 V (Max), V_IH = 2 V (Min)
D CMOS Input Compatibility, I_l v 1 mA at V_OL,
V_OH
M OR PW PACKAGE
(TOP VIEW)
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND ¹⁰
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 _CP
description/ordering information
The CD74HCT574 is an octal D-type flip-flop with 3-state outputs and the capability to drive 15 LSTTL loads.
The eight edge-triggered flip-flops enter data into their registers on the low-to-high transition of the clock (CP).
The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is
high, the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − M
Tape and reel
−40°C to 125°C
TSSOP − PW Tape and reel
CD74HCT574QM96EP
CD74HCT574QPWREP
HCT574EP
HCT574EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2004, Texas Instruments Incorporated
1