BQ24070RHLRG4 Datasheet, PDF (6/31 Pages) Texas Instruments – SINGLE-CHIP LI-ION CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

bq24070
bq24071
SLUS694F – MARCH 2006 – REVISED DECEMBER 2009
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ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ T_J ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MODE INPUT
V_IL
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied when
low.
0.975
1
1.025
V
V_IH
I_IL
TIMERS
High-level input voltage
Low-level input current, Mode
Input R_Mode sets external hysteresis
V_IL + .01
–1
V_IL + .024
V
μA
K_(TMR)
R_(TMR) ⁽¹⁰⁾
t_(PRECHG)
I_(FAULT)
Timer set factor
External resistor limits
Precharge timer
Timer fault recovery pullup from
OUT to BAT
t_(CHG) = K_(TMR) × R_(TMR)
0.313
0.360
0.414
s/Ω
30
100
kΩ
0.09 ×
t_(CHG)
0.10 × t_(CHG) 0.11 × t_(CHG)
s
1
kΩ
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)
V_(SLPENT) ⁽¹¹⁾
V_(SLPEXIT) ⁽¹¹⁾
Sleep-mode entry threshold
Sleep-mode exit threshold
V_(UVLO) ≤ V_I(BAT) ≤ V_O(BAT-REG),
No t_(BOOT-UP) delay
V_(UVLO) ≤ V_I(BAT) ≤ V_O(BAT-REG),
No t_(BOOT-UP) delay
V_VCC ≥
V_I(BAT)
+190 mV
V_VCC ≤
V_I(BAT)
+125 mV
V
t_(DEGL)
De-glitch time for sleep mode⁽¹²⁾
R_(TMR) = 50 kΩ,
V_(IN) decreasing below threshold, 100-ns fall
time, 10-mv overdrive
22.5
ms
START-UP CONTROL BOOT-UP
t_(BOOT-UP)
Boot-up time
On the first application of input with Mode
Low
120
150
180
ms
SWITCHING POWER SOURCE TIMING
t_SW-BAT
Switching power source from input
to battery
THERMAL SHUTDOWN REGULATION⁽¹³⁾
When input applied. Measure from:
[PG: Lo → Hi to I_(IN) > 5 mA],
I_(OUT) = 100 mA,
R_TRM = 50 K
50
μs
T_(SHTDWN)
T_J(REG)
UVLO
Temperature trip
Thermal hysteresis
Temperature regulation limit
T_J (Q1 and Q3 only)
T_J (Q1 and Q3 only)
T_J (Q2)
155
30
°C
115
135
V_(UVLO)
Undervoltage lockout
Hysteresis
Decreasing V_CC
2.45
2.50
2.65
V
27
mV
V_REF OUTPUT
V_O(VREF)
Output regulation voltage
Regulation accuracy⁽¹⁴⁾
Active only if AC or USB is present,
V_I(OUT) ≥ V_O(VREF) + (I_O(VREF) × R_DS(on))
–5%
3.3
V
5%
I_O(VREF)
R_DS(on)
C_(OUT) ⁽¹⁵⁾
Output current
On resistance
Output capacitance
OUT to V_REF
20
mA
50
Ω
1
μF
(10) To disable the fast-charge safety timer and charge termination, tie TMR to the V_REF pin. Tying the TMR pin high changes the timing
resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed specification. The TMR
pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become
active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by
the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum
time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(11) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).
(12) Does not declare sleep mode until after the de-glitch time and implement the needed power transfer immediately according to the
switching specification.
(13) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
(14) In standby mode (CE low) the accuracy is ±10%.
(15) V_REF output capacitor not required, but one with a value of 0.1 μF is recommended.
6
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