TMS570LS0432_15 Datasheet, PDF (59/110 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
Figure 6-13 shows a typical high-level block diagram for one of the four compares inside the RTI module.
Each of the four compares are identical.
31
0
Update
compare
RTIUDCPy
From counter
block 0
From counter
block 1
+
31
0
Compare
RTICOMPy
Compare
control
INTy
Figure 6-13. Compare Block Diagram
6.16.3 Clock Source Options
The RTI module uses the RTICLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.
For more information, on the clock sources see Table 6-8 and Table 6-12.
6.17 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.
The error condition is handled based on a fixed severity level assigned to it. Any severe error condition
can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used
as an indicator to an external monitor circuit to put the system into a safe state.
6.17.1 Features
The features of the Error Signaling Module are:
• 128 interrupt/error channels are supported, divided into 3 different groups
– 64 channels with maskable interrupt and configurable error pin behavior
– 32 error channels with nonmaskable interrupt and predefined error pin behavior
– 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability
6.17.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 6-26 shows the channel assignment for each group.
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System Information and Electrical Specifications
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