TMS570LS0432_15 Datasheet, PDF (53/110 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
6.12 Tightly Coupled RAM Interface Module
Figure 6-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4 CPU.
Cortex-R4
B0
TCM
VBUSP I/F PMT I/F
EVEN Address
TCM BUS
64 Bit data bus
Upper 32 bits data &
4 ECC bits
TCRAM
Interface 1
Lower 32 bits data &
4 ECC bits
36 Bit
3wR6iA3wRdMB6ew_{RiAditAMBiediM}et
36 Bit
3w6i3wdB6ew_RiditA^Biedi_Met
RARMAM
B1
TCM
ODD Address
TCM BUS
64 Bit data bus
Upper 32 bits data &
4 ECC bits
TCRAM
Interface 2
Lower 32 bits data &
4 ECC bits
36 Bit
36³B^6wi^Btidiet
wiwdeR^idA^eM
RARMAM
36 Bit
36³B^6wi^Btidiet
wRiAwRdMeR^iAdA_MeM
VBUSP I/F PMT I/F
Figure 6-11. TCRAM Block Diagram
6.12.1 Features
The features of the Tightly Coupled RAM (TCRAM) module are:
• Acts as slave to the BTCM interface of the Cortex-R4 CPU
• Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single-bit or multibit error interrupts
• Stores addresses for single-bit and multibit errors
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits
• No support for bit-wise RAM accesses
6.12.2 TCRAMW ECC Support
The TCRAMW passes on the ECC code for each data read by the Cortex-R4 CPU from the RAM. It also
stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The
TCRAMW monitors the CPU's event bus and provides registers for indicating single-bit and multibit errors
and also for identifying the address that caused the single-bit or multibit error. The event signaling and the
ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see the device Technical Reference Manual.
6.13 Parity Protection for Accesses to peripheral RAMs
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
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System Information and Electrical Specifications
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