TMS570LS0432_15 Datasheet, PDF (55/110 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
6.14.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware
Initialization mechanism in the System module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers refer to the device Technical Reference Manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-23.
Table 6-23. Memory Initialization
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
MSINENA REGISTER
BIT NO.⁽¹⁾
RAM
MIBSPI1 RAM
0x08000000
0x08007FFF
0
0xFF0E0000
0xFF0FFFFF
7 ⁽²⁾
DCAN2 RAM
0xFF1C0000
0xFF1DFFFF
6
DCAN1 RAM
0xFF1E0000
0xFF1FFFFF
5
MIBADC RAM
0xFF3E0000
0xFF3FFFFF
8
N2HET RAM
0xFF460000
0xFF47FFFF
3
HTU RAM
0xFF4E0000
0xFF4FFFFF
4
VIM RAM
0xFFF82000
0xFFF82FFF
2
(1) Unassigned register bits are reserved.
(2) The MibSPI1 module performs an initialization of the transmit and receive RAMs as soon as the module is brought out of reset using the
SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using
the system module auto-initialization method.
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System Information and Electrical Specifications
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