TMS320DA707B Datasheet, PDF (59/91 Pages) Texas Instruments – Floating-Point Digital Signal Processors

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Aureus TMS320DA707, TMS320DA707B, TMS320DA787B
Floating-Point Digital Signal Processors
SPRS279E – JULY 2005 – REVISED FEBRUARY 2008
Table 3-24. Additional⁽¹⁾ SPI Slave Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
MIN
MAX UNIT
25 t_{d(SCSL_SPC)S}
Required delay from SPIx_SCS asserted at slave to first
SPIx_CLK edge at slave.
P
ns
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5t_c(SPC)M + P + 10
Required delay from final
Polarity = 0, Phase = 1,
from SPIx_CLK falling
P + 10
26 t_{d(SPC_SCSH)S}
SPIx_CLK edge before
SPIx_SCS is deasserted.
Polarity = 1, Phase = 0,
from SPIx_CLK rising
0.5t_c(SPC)M + P + 10
ns
Polarity = 1, Phase = 1,
from SPIx_CLK rising
P + 10
27
t_{ena(SCSL_SOMI)S}
Delay from master asserting SPIx_SCS to slave driving
SPIx_SOMI valid
P + 15 ns
28
t_{dis(SCSH_SOMI)S}
Delay from master deasserting SPIx_SCS to slave 3-stating
SPIx_SOMI
P + 15 ns
29
t_{ena(SCSL_ENA)S}
Delay from master deasserting SPIx_SCS to slave driving
SPIx_ENA valid
15 ns
Polarity = 0, Phase = 0,
from SPIx_CLK falling
2P + 15
30 t_{dis(SPC_ENA)S}
Delay from final clock receive
edge on SPIx_CLK to slave
3-stating or driving high
SPIx_ENA. ⁽⁴⁾
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
2P + 15
ns
2P + 15
Polarity = 1, Phase = 1,
from SPIx_CLK falling
2P + 15
(1) These parameters are in addition to the general timings for SPI slave modes (Table 3-18).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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Peripheral and Electrical Specifications
59