TMS320DA707B Datasheet, PDF (48/91 Pages) Texas Instruments – Floating-Point Digital Signal Processors

Aureus TMS320DA707, TMS320DA707B, TMS320DA787B
Floating-Point Digital Signal Processors
SPRS279E – JULY 2005 – REVISED FEBRUARY 2008
Table 3-15. McASP Switching Characteristics⁽¹⁾
NO.
PARAMETER
Cycle time, AHCLKR internal, AHCLKR output
9
t_c(AHCKRX)
Cycle time, AHCLKR external, AHCLKR output
Cycle time, AHCLKX internal, AHCLKX output
Cycle time, AHCLKX external, AHCLKX output
Pulse duration, AHCLKR internal, AHCLKR output
10
t_w(AHCKRX)
Pulse duration, AHCLKR external, AHCLKR output
Pulse duration, AHCLKX internal, AHCLKX output
Pulse duration, AHCLKX external, AHCLKX output
Cycle time, ACLKR internal, ACLKR output
11
t_c(ACKRX)
Cycle time, ACLKR external, ACLKR output
Cycle time, ACLKX internal, ACLKX output
Cycle time, ACLKX external, ACLKX output
Pulse duration, ACLKR internal, ACLKR output
12
t_w(ACKRX)
Pulse duration, ACLKR external, ACLKR output
Pulse duration, ACLKX internal, ACLKX output
Pulse duration, ACLKX external, ACLKX output
Delay time, ACLKR internal, AFSR output
Delay time, ACLKX internal, AFSX output
Delay time, ACLKR external input, AFSR output
Delay time, ACLKX external input, AFSX output
Delay time, ACLKR external output, AFSR output
13
t_d(ACKRX-FRX)
Delay time, ACLKX external output, AFSX output
Delay time, ACLKR internal, AFSR output
Delay time, ACLKX internal, AFSX output
Delay time, ACLKR external input, AFSR output
Delay time, ACLKX external input, AFSX output
Delay time, ACLKR external output, AFSR output
Delay time, ACLKX external output, AFSX output
Delay time, ACLKX internal, AXRn output
14
t_{d(ACLKX-AXRV)}
Delay time, ACLKX external input, AXRn output
Delay time, ACLKX external output, AXRn output
Disable time, ACLKX internal, AXRn output
15
t_{dis(ACKX-AXRHZ)}
Disable time, ACLKX external input, AXRn output
Disable time, ACLKX external output, AXRn output
(1) ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR.
(3) AHX - Cycle time, AHCLKX.
(4) P = SYSCLK2 period
(5) AR - ACLKR period.
(6) AX - ACLKX period.
MIN
20
20
20
20
(AHR/2) – 2.5⁽²⁾
(AHR/2) – 2.5⁽²⁾
(AHX/2) – 2.5⁽³⁾
(AHX/2) – 2.5⁽³⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
(AR/2) – 2.5⁽⁵⁾
(AR/2) – 2.5⁽⁵⁾
(AX/2) – 2.5⁽⁶⁾
(AX/2) – 2.5⁽⁶⁾
–1
–1
0
0
0
0
–1
0
0
–3
–3
–3
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MAX UNIT
ns
ns
ns
ns
5
5
10
10
10
10
ns
5
10 ns
10
10
10 ns
10
48
Peripheral and Electrical Specifications
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