ADS54J20 Datasheet, PDF (59/81 Pages) Texas Instruments – Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter

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8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
ADS54J20
SBAS766A – MAY 2016 – REVISED MAY 2016
Figure 115. Register 1h
7
6
5
4
3
SYNC REG SYNC REG EN
JESD FILTER
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
2
1
0
JESD MODE
R/W-01h
Table 51. Register 1h Field Descriptions
Bit Field
7
SYNC REG
6
SYNC REG EN
5-3 JESD FILTER
2-0 JESD MODE
Type
R/W
Reset
0h
R/W
0h
R/W
0h
R/W
01h
Description
This bit is the register control for the sync request.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters; the SYNC
REG EN register bit must also be set to 1
This bit enables register control for the sync request.
0 = Use the SYNC pin for sync requests
1 = Use the SYNC REG register bit for sync requests
These bits and the JESD MODE bits set the correct LMFS
configuration for the JESD interface. The JESD FILTER setting
must match the configuration in the decimation filter page.
000 = Filter bypass mode
See Table 52 for valid combinations for register bits JESD FILTER
along with JESD MODE.
These bits select the number of serial JESD output lanes per ADC.
The JESD PLL MODE register bit located in the JESD analog page
must also be set accordingly.
001 = Default after reset(Eight active lanes)
See Table 52 for valid combinations for register bits JESD FILTER
along with JESD MODE.
Table 52. Valid Combinations for JESD FILTER and JESD MODE Bits
REGISTER BIT JESD FILTER
000
000
000
111
110
110
100
111
100
REGISTER BIT JESD MODE
100
010
001
001
001
010
001
010
010
DECIMATION FACTOR
No decimation
No decimation
No decimation
(default after reset)
4X (IQ)
2X
2X
4X
4X (IQ)
4X
NUMBER OF ACTIVE LANES
PER DEVICE
Four lanes are active
Four lanes are active
Eight lanes are active
Four lanes are active
Four lanes are active
Two lanes are active
Two lanes are active
Two lanes are active
One lane is active
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