ADS54J20 Datasheet, PDF (31/81 Pages) Texas Instruments – Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter

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ADS54J20
SBAS766A – MAY 2016 – REVISED MAY 2016
8.3.5 Power-Down Mode
The ADS54J20 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 5. See the master page registers in Table 14 for further details.
Table 5. Register Addresses for Power-Down Modes
REGISTER
ADDRESS
COMMENT
REGISTER DATA
A[7:0] (Hex)
7
6
5
4
3
2
1
0
MASTER PAGE (80h)
20
PDN ADC CHA
PDN ADC CHB
MASK 1
21
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
23
PDN ADC CHA
PDN ADC CHB
MASK 2
24
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
26
CONFIG
GLOBAL
PDN
OVERRIDE PDN MASK
PDN PIN
SEL
0
0
0
0
0
53
0
MASK
SYSREF
0
0
0
0
0
0
55
0
0
0
PDN MASK
0
0
0
0
To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,
when JESD is required to remain active when putting the device in power-down, the ADC and analog buffer can
be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN
MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 6
shows the power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF
CHx register bits.
REGISTER BIT
Default
GBL PDN = 1
GBL PDN = 0,
PDN ADC CHx = 1
(x = A or B)
GBL PDN = 0,
PDN BUFF CHx = 1
(x = A or B)
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A or B)
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A and B)
Table 6. Power Consumption in Different Power-Down Settings
COMMENT
After reset, with a full-scale input signal to both
channels
The device is in a complete power-down state
The ADC of one channel is powered down
I_AVDD3V
(mA)
247
3
I_AVDD
(mA)
260
6
206
166
I_DVDD
(mA)
137
23
97
I_IOVDD
(mA)
382
192
367
TOTAL
POWER
(W)
1.94
0.28
1.54
The input buffer of one channel is powered down
195
258
137
381
1.78
The ADC and input buffer of one channel are
powered down
152
166
97
363
1.37
The ADC and input buffer of both channels are
powered down
55
70
56
356
0.81
Copyright © 2016, Texas Instruments Incorporated
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