ADS54J20 Datasheet, PDF (58/81 Pages) Texas Instruments – Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter

ADS54J20
SBAS766A – MAY 2016 – REVISED MAY 2016
8.5.3.5 JESD Digital Page (6900h) Registers
8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
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Figure 114. Register 0h
7
6
5
4
CTRL K
0
0
TESTMODE
EN
R/W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
FLIP ADC
DATA
R/W-0h
2
LANE ALIGN
R/W-0h
1
FRAME ALIGN
R/W-0h
0
TX LINK DIS
R/W-0h
Table 50. Register 0h Field Descriptions
Bit Field
7
CTRL K
6-5 0
4
TESTMODE EN
3
FLIP ADC DATA
2
LANE ALIGN
1
FRAME ALIGN
0
TX LINK DIS
Type
R/W
Reset
0h
W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
Description
This bit is the enable bit for a number of frames per multiframe.
0 = Default is five frames per multiframe
1 = Frames per multiframe can be set in register 06h
Must write 0
This bit generates the long transport layer test pattern mode, as
per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
0 = Normal operation
1 = Output data order is reversed: MSB to LSB.
This bit inserts the lane alignment character (K28.3) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
This bit inserts the lane alignment character (K28.7) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is deasserted.
0 = Normal operation
1 = ILA disabled
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