TM4C1233D5PM Datasheet, PDF (585/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233D5PM Microcontroller
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a μDMA transfer.
Note: The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type RW, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
Type RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARBSIZE
XFERSIZE
XFERMODE
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:30
Name
DSTINC
Type
RW
Reset
-
Description
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Value Description
0x0 Byte
Increment by 8-bit locations
0x1 Half-word
Increment by 16-bit locations
0x2 Word
Increment by 32-bit locations
0x3 No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel
June 12, 2014
585
Texas Instruments-Production Data