TM4C1233D5PM Datasheet, PDF (480/1214 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
7.4.5
7.5
3. Enable the external wake and start the hibernation sequence by writing 0x0000.0052 to the
HIBCTL register at offset 0x010.
RTC or External Wake-Up from Hibernation
1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.
2. Write the required RTC match value to the HIBRTCM0 register at offset 0x004 and the RTCSSM
field in the HIBRTCSS register at offset 0x028.
3. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. This write causes
the 15-bit sub seconds counter to be cleared.
4. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F.
5. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005B
to the HIBCTL register at offset 0x010.
Register Map
Table 7-3 on page 480 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must
be enabled before the registers can be programmed (see page 330). There must be a delay of 3
system clocks after the Hibernation module clock is enabled before any Hibernation module registers
are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing
any other Hibernation module register.
Note:
The Hibernation module registers are on the Hibernation module clock domain and have
special timing requirements. Software should make use of the WRC bit in the HIBCTL register
to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted
write access is ignored. See “Register Access Timing” on page 470.
Important: The Hibernation module registers are reset under two conditions:
1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear).
2. A cold POR occurs when both the V_DD and V_BAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Table 7-3. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x00C HIBRTCLD
0x010 HIBCTL
0x014 HIBIM
RO
0x0000.0000 Hibernation RTC Counter
RW
0xFFFF.FFFF Hibernation RTC Match 0
RW
0x0000.0000 Hibernation RTC Load
RW
0x8000.2000 Hibernation Control
RW
0x0000.0000 Hibernation Interrupt Mask
See
page
482
483
484
485
489
480
June 12, 2014
Texas Instruments-Production Data