TM4C1233D5PM Datasheet, PDF (177/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233D5PM Microcontroller
Register 78: Memory Management Fault Address (MMADDR), offset 0xD34
Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 170).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type RW, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
ADDR
Type
RW
Reset
-
Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
June 12, 2014
177
Texas Instruments-Production Data