TM4C1233D5PM Datasheet, PDF (1112/1214 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
4
3
2
1
Name
FLUSH
DATAERR
OVER
FULL
Type
RW
RO
RW
RO
Reset
0
Description
Flush FIFO
Value Description
0 No effect.
1 Flushes the next packet from the endpoint receive FIFO. The
FIFO pointer is reset and the RXRDY bit is cleared.
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared. Note that if the FIFO is double-buffered, FLUSH may have
to be set twice to completely clear the FIFO.
Important: ^{This bit should only be set when the RXRDY bit is set. At}
other times, it may cause data to be corrupted.
0
Data Error
Value Description
0 Normal operation.
1 Indicates that RXRDY is set and the data packet has a CRC or
bit-stuff error.
This bit is cleared when RXRDY is cleared.
Note: This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
0
Overrun
Value Description
0 No overrun error.
1 Indicates that an OUT packet cannot be loaded into the receive
FIFO.
Software must clear this bit.
Note: This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
0
FIFO Full
Value Description
0 The receive FIFO is not full.
1 No more packets can be loaded into the receive FIFO.
1112
Texas Instruments-Production Data
June 12, 2014