TMS320F28055_16 Datasheet, PDF (58/150 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797B – NOVEMBER 2012 – REVISED JULY 2014
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6.5 VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the V_DD voltage from the V_DDIO supply. This feature eliminates the
cost and space of a second external regulator on an application board. Additionally, internal power-on
reset (POR) and brown-out reset (BOR) circuits monitor both the V_DD and V_DDIO rails during power-up and
run mode.
6.5.1 On-chip VREG
A linear regulator generates the core voltage (V_DD) from the V_DDIO supply. Therefore, although capacitors
are required on each V_DD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
6.5.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the V_DDIO and V_DDA pins. In this case, the V_DD voltage needed by
the core logic will be generated by the VREG. Each V_DD pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the V_DD pins.
6.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the V_DD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
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Detailed Description
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TMS320F28050