TMS320F28055_16 Datasheet, PDF (42/150 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797B – NOVEMBER 2012 – REVISED JULY 2014
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Disclaimer
Dual Code Security Module Disclaimer
THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS
(TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM
TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE
FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
6.1.11 Peripheral Interrupt Expansion Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible
96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed
into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector
stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save
critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is
controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE
block.
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Detailed Description
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