TMS320F28055_16 Datasheet, PDF (102/150 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797B – NOVEMBER 2012 – REVISED JULY 2014
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SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
6
7
Master out data Is valid
10
11
Master in data
must be valid
3
Data Valid
SPISTE^(A)
A. In the master mode, SPISTE goes active 0.5t_c(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t_c(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-30. SPI Master Mode External Timing (Clock Phase = 1)
102 Detailed Description
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