MSP430F532X Datasheet, PDF (58/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F532x
SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note ⁽¹⁾, Figure 13 and Figure 14)
PARAMETER
t_STE,LEAD STE lead time, STE low to clock
TEST CONDITIONS
PMMCOREV = 0
PMMCOREV = 3
V_CC
1.8 V
3V
2.4 V
3V
MIN TYP
11
8
7
6
t_STE,LAG STE lag time, Last clock to STE high
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3
3V
3
2.4 V
3
3V
3
t_STE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
t_STE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
t_SU,SI
SIMO input data setup time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
5
3V
5
2.4 V
2
3V
2
t_HD,SI
SIMO input data hold time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
5
3V
5
2.4 V
5
3V
5
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
PMMCOREV = 0
UCLK edge to SOMI valid,
C_L = 20 pF
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
PMMCOREV = 0
C_L = 20 pF
PMMCOREV = 3
1.8 V
18
3V
12
2.4 V
10
3V
8
MAX UNIT
ns
ns
ns
ns
66
ns
50
36
ns
30
30
ns
23
16
ns
13
ns
ns
ns
ns
76
ns
60
44
ns
40
ns
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and Figure 12.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 11
and Figure 12.
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