LMK04610 Datasheet, PDF (58/124 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

LMK04610
SNAS699 – JANUARY 2017
www.ti.com
Register Maps (continued)
Table 26. Register Map (continued)
ADDRESS
DATA
0x6E
PLL2_BYP_SYNC PLL2_BYP_SYNC_ PLL2_EN_BYP_BU PLL2_EN_BUF_SY PLL2_EN_BUF_SY PLL2_EN_BUF_OS PLL2_EN_BUF_CL PLL2_EN_BUF_CL
_TOP
BOTTOM
F
NC_TOP
NC_BOTTOM
COUT
K_TOP
K_BOTTOM
0x6F
RSRVD
PLL2_RDIV_SWRS PLL2_NDIV_SWRS
T
T
PLL2_SWRST
0x70
PLL2_C4_LF_SEL[3:0]
PLL2_R4_LF_SEL[3:0]
0x71
PLL2_C3_LF_SEL[3:0]
PLL2_R3_LF_SEL[3:0]
0x72
PLL2_PROP[7:0]
0x73
PLL2_NDIV[15:8]
0x74
PLL2_NDIV[7:0]
0x75
PLL2_RDIV[15:8]
0x76
PLL2_RDIV[7:0]
0x77
PLL2_STRG_INITVAL[15:8]
0x78
PLL2_STRG_INITVAL[7:0]
0x7D
RSRVD
RAILDET_UPP[5:0]
0x7E
RSRVD
RAILDET_LOW[5:0]
0x7F
RSRVD
PLL2_AC_CAL_EN
PLL2_PD_AC
PLL2_IDACSET_RECAL[1:0]
PLL2_AC_REQ PLL2_FAST_ACAL
0x80
PLL2_INTG[7:0]
0x81
RSRVD
PLL2_AC_THRESHOLD[4:0]
0x82
RSRVD
PLL2_AC_STRT_THRESHOLD[4:0]
0x83
PLL2_AC_CMP_WAIT[3:0]
PLL2_AC_INIT_WAIT[3:0]
0x84
RSRVD
PLL2_AC_JUMP_STEP[3:0]
0x85
PLL2_LD_WNDW_SIZE[7:0]
0x86
PLL2_LD_WNDW_SIZE_INITIAL[7:0]
0x87
PLL2_LOCKDET_CYC_CNT[23:16]
0x88
PLL2_LOCKDET_CYC_CNT[15:8]
0x89
PLL2_LOCKDET_CYC_CNT[7:0]
0x8A
PLL2_LOCKDET_CYC_CNT_INITIAL[23:16]
0x8B
PLL2_LOCKDET_CYC_CNT_INITIAL[15:8]
0x8C
PLL2_LOCKDET_CYC_CNT_INITIAL[7:0]
0x8D
SPI_EN_THREE_
WIRE_IF
RSRVD
SPI_SDIO_OUTPUT SPI_SDIO_OUTPUT SPI_SDIO_OUTPUT SPI_SDIO_EN_PUL SPI_SDIO_EN_PUL
_MUTE
_INV
_WEAK_DRIVE
LUP
LDOWN
0x8E
RSRVD
SPI_SCL_EN_PULL SPI_SCL_EN_PULL SPI_SCS_EN_PULL SPI_SCS_EN_PULL
UP
DOWN
UP
DOWN
58
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