LMK04610 Datasheet, PDF (12/124 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

LMK04610
SNAS699 – JANUARY 2017
www.ti.com
7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V; 1.7 V < VDD_IO, VDD_OSC, VDDO_x <
3.465 V; –40°C < T_A < 85°C and T_PCB ≤ 105°C. Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE,
VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, T_A = 25°C, at the Recommended Operating Conditions and are
not assured.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
HSDS 4 mA
–166
HSDS 6 mA
–166
L(f)_{CLKout/OSCout}
NF
Noise floor
20-MHz offset
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2⁽¹⁾
122.88 MHz
HSDS 8 mA
HCSL 16 mA
OSCout, HSDS 4
mA
OSCout, HSDS 8
mA
–166
–165
–161
–161
dBc/Hz
OSCout, LVCMOS
–156
L(f)_CLKoutNF,AD
LY
Noise floor with analog delay enabled
20-MHz offset
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2⁽¹⁾
122.88 MHz,
maximum analog
delay setting
HSDS 4 mA
HSDS 6 mA
HSDS 8 mA
HCSL 16 mA
–151
–151
–151
–151
dBc/Hz
Offset = 100 Hz
–97
L(f)_CLKoutPN
SSB phase noise⁽²⁾
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2
(1) (3)
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 800 kHz
Offset = 1 MHz
–126
–139
–147
–158
–159
dBc/Hz
HSDS 8 mA
Offset = 10 MHz
HCSL 16 mA
–166
–165
Offset = 100 Hz
–97
L(f)_OSCoutPN
SSB phase noise
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2
(1) (3)
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
HSDS 4 mA
–136
–148
–157
–160
dBc/Hz
Offset = 10 MHz HSDS 8 mA
–160
J_CLKout
f_CLKout = 122.88 MHz
Integrated RMS jitter
≤ 100-Hz loop bandwidth for PLL1
400 kHz Loop Bandwidth for PLL2 ⁽¹⁾
(4)
HSDS 8 mA, BW = 100 Hz to 20 MHz
HSDS 8 mA, BW = 10 kHz to 20 MHz
HCSL 16 mA, BW = 100 Hz to 20 MHz
HCSL 16 mA, BW = 10 kHz to 20 MHz
160
75
fs rms
160
75
(1) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
(2) Phase noise defined in dual loop mode and in single PLL mode, if OSCin is used as ref input
(3) The input is configured to either a full swing AC-coupled, single-ended signal or a LVDS like AC-coupled differential signal. The input
frequency is 122.88 MHz. VDD_IN is at 1.8 V.
(4) PLL1 and PLL2 settings optimized to meet multi-carrier GSM phase noise specifications. For RMS jitter optimized settings, see PLL1
and PLL2.
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