LMK04610 Datasheet, PDF (1/124 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
LMK04610
SNAS699 – JANUARY 2017
LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner
With Dual Loop PLLs
1 Features
•1 Dual Loop PLL Architecture
– 65-fs RMS Jitter (10 kHz to 20 MHz)
– 85-fs RMS Jitter (100 Hz to 20 MHz)
– –165-dBc/Hz Noise Floor at 122.88 MHz
• JEDEC JESD204B Support
– Single Shot, Pulsed, and Continuous SYSREF
• 10 or 16 Differential Output Clocks in 6 or 8
Frequency Groups
– Programmable Output Swing Between 700
mVpp to 1600 mVpp
– Each Output Pair Can be Configured to
SYSREF Clock Output
– 16-Bit Channel Divider
– Minimum SYSREF Frequency of 25 kHz
– Maximum Output Frequency of 2 GHz
– Precision Digital Delay, Dynamically Adjustable
– Digital Delay (DDLY) of ½ × Clock
Distribution Path Frequency (2 GHz
Maximum)
– 60-ps Step Analog Delay
– 50 % Duty Cycle Output Divides, 1 to 65535
(Even and Odd)
• 2 or 4 Reference Inputs
– Holdover Mode, When Inputs are Lost
– Automatic and Manual Switch-Over Modes
– Loss-of-Signal (LOS) Detection
• 0.88-W Typical Power Consumption With 10
Outputs Active
• Operates Typically From a 1.8-V (Outputs, Inputs)
and 3.3-V Supply (Digital, PLL1, PLL2_OSC,
PLL2 Core)
• Fully Integrated Programmable Loop Filter
• PLL2
– PLL2 Phase Detector Rate Up to 250 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO
• Internal Power Conditioning: Better Than –70-dBc
PSRR (50-mVpp Ripple From 100 kHz to 1 MHz)
for 122.88-MHz Differential Outputs
• 3- or 4-Wire SPI Interface (3-Wire is Default)
• –40ºC to +85ºC Industrial Ambient Temperature
Range
• Supports 105ºC PCB Temperature (Measured at
Thermal Pad)
• LMK04610: 8-mm × 8-mm VQFN-56 Package
With 0.5-mm Pitch
2 Applications
• Wireless Infrastructure Like LTE-BTS, Small Cells,
Remote Radio Units (RRU)
• Data Converter and Integrated Transceiver
Clocking
• Networking, SONET/SDH, DSLAM
• Medical, Video, Military, and Aerospace
• Test and Measurement
• JESD204B Applications
3 Description
The LMK0461x device family is the industry's highest
performance and lowest power clock conditioner with
JEDEC JESD204B support.
Device Information⁽¹⁾
PART NUMBER
VCO FREQUENCY
LMK04610
5.8 to 6.2 GHz
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Recovered
³GLUW\´ FORFN RU
clean clock
VCXO
CLKin0
Backup
Reference
Clock
CLKin1
OSCout
LMK04610
CLKout9
CLKout10
LMX2582
PLL+VCO
FPGA
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
ADC
CLKout1 &
CLKout2
CLKout3 &
CLKout4
CLKout5 &
CLKout6
CLKout7 &
CLKout8
DDAACC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.