LMK04610 Datasheet, PDF (111/124 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

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9.6.2.193 PLL2_CTRL4
PLL2 CTRL4 Register sets PLL2 configuration. Return to Register Map.
BIT NO.
[7:4]
[3]
[2:0]
FIELD
RSRVD
PLL2_PFD_DIS_SAMPLE
PLL2_PROG_PFD_RESET[2
:0]
Table 219. Register – 0x150
TYPE
-
RW
RESET
-
0
RW
0x0
LMK04610
SNAS699 – JANUARY 2017
DESCRIPTION
Reserved.
Disable PFD Sampling.
Programmable PFD reset.
9.6.2.194 PLL2_CTRL5
PLL2 CTRL5 Register sets PLL2 configuration. Return to Register Map.
BIT NO.
[7:5]
[4]
[3]
[2]
[1:0]
FIELD
RSRVD
PLL2_RFILT
RSRVD
PLL2_CP_EN_SAMPLE_BY
P
PLL2_CPROP[1:0]
Table 220. Register – 0x151
TYPE
-
RESET
-
RW
0
-
-
DESCRIPTION
Reserved.
0-> 9.2 kΩ
1->4.7 kΩ
Reserved.
RW
0
Bypass PLL2 Chargepump sampling.
RW
0x0
Set Cap prior Sampling.
9.6.2.195 PLL2_CTRL6
PLL2 CTRL6 Register sets PLL2 configuration. Return to Register Map.
BIT NO.
[7:4]
[3]
[2:0]
FIELD
RSRVD
PLL2_EN_FILTER
PLL2_CSAMPLE[2:0]
Table 221. Register – 0x152
TYPE
-
RW
RW
RESET
-
0
0x0
DESCRIPTION
Reserved.
Enable PLL2 Chargepump Filter.
PLL2 Set Cap After sampling.
9.6.2.196 PLL2_CTRL7
PLL2 CTRL7 Register sets PLL2 configuration. Return to Register Map.
BIT NO.
[7:5]
[4:0]
FIELD
RSRVD
PLL2_CFILT
Table 222. Register – 0x153
TYPE
-
RW
RESET
-
0
DESCRIPTION
Reserved.
0 to 124 pF in 4-pF steps
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