ADC12DJ3200 Datasheet, PDF (57/111 Pages) Texas Instruments – 6.4-GSPS Single Channel or 3.2-GSPS Dual Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)

www.ti.com
ADC12DJ3200
SLVSD97 – MAY 2017
7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data
out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin.
7.5.1.1 SCS
This signal must be asserted low to access a register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
7.5.1.2 SCLK
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.
7.5.1.3 SDI
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write
(R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and hold times with respect
to the SCLK must be observed (see Timing Requirements).
7.5.1.4 SDO
The SDO signal provides the output data requested by a read command. This output is high impedance during
write bus cycles and during the read bit and register address portion of read bus cycles.
Each register access consists of 24 bits, as shown in Figure 13. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are
the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during
this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in
Figure 13.
Single Register Access
SCS
SCLK
SDI
1
8
16 17
24
R/W A14 A13 A12 A11 A10 A9
Command Field
A8 A7 A6 A5
A4 A3 A2
Data Field
A1 A0 D7 D6 D5 D4 D3 D2
D1 D0
SDO
(read mode)
High Z
D7 D6 D5
Data Field
D4 D3 D2
D1 D0
Figure 13. Serial Interface Protocol - Single Read / Write
High Z
7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (User
SPI Configuration Register (address = 0x010) [reset = 0x00]). The streaming mode transaction details are shown
in Figure 14.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: ADC12DJ3200
Submit Documentation Feedback
57