English
Language : 

ADC12DJ3200 Datasheet, PDF (18/111 Pages) Texas Instruments – 6.4-GSPS Single Channel or 3.2-GSPS Dual Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
ADC12DJ3200
SLVSD97 – MAY 2017
www.ti.com
Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS - SINGLE CHANNEL MODE
CER
Code error rate
10–18
errors/sam
ple
No input, foreground calibration,
NOISEDC DC input noise standard deviation
excludes DC offset, includes fixed
interleaving spurs (Fs/2 and Fs/4
3.5
LSB
spurs)
NSD
Noise spectral density, no input
signal, excludes fixed interleaving
spurs (Fs/2 and Fs/4 spur)
Maximum full-scale voltage
(FS_RANGE_A = 0xFFFF) setting,
foreground calibration
Default full-scale voltage
(FS_RANGE_A = 0xA000) setting,
foreground calibration
-154.6
-153.1
dBFS/Hz
Maximum full-scale voltage
(FS_RANGE_A = 0xFFFF) setting,
20.7
foreground calibration
NF
Noise figure, no input, ZS = 100 Ω Default full-scale voltage
dB
(FS_RANGE_A = 0xA000) setting,
19.9
foreground calibration
fIN = 347 MHz, AIN = –1 dBFS
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
56.6
57.5
fIN = 997 MHz, AIN = –1 dBFS
56.3
SNR
Signal to noise ratio, large signal,
excluding DC, HD2, HD3 and
fIN = 2482 MHz, AIN = –1 dBFS
52
55.3
interleaving spurs
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
56.1
foreground calibration
dBFS
SNR
SINAD
ENOB
Signal to noise ratio, small signal,
excluding DC, HD2, HD3 and
interleaving spurs
Signal to noise and distortion ratio,
large signal, excluding DC and FS/2
fixed spurs
Effective number of bits, large
signal, excluding DC and FS/2 fixed
spurs
fIN = 4997 MHz, AIN = –1 dBFS
fIN = 6397 MHz, AIN = –1 dBFS
fIN = 8197 MHz, AIN = –1 dBFS
fIN = 347 MHz, AIN = –16 dBFS
fIN = 997 MHz, AIN = –16 dBFS
fIN = 2482 MHz, AIN = –16 dBFS
fIN = 4997 MHz, AIN = –16 dBFS
fIN = 6397 MHz, AIN = –16 dBFS
fIN = 8197 MHz, AIN = –16 dBFS
fIN = 347 MHz, AIN = –1 dBFS
fIN = 997 MHz, AIN = –1 dBFS
fIN = 2482 MHz, AIN = –1 dBFS
fIN = 4997 MHz, AIN = –1 dBFS
fIN = 6397 MHz, AIN = –1 dBFS
fIN = 8197 MHz, AIN = –1 dBFS
fIN = 347 MHz, AIN = –1 dBFS
fIN = 997 MHz, AIN = –1 dBFS
fIN = 2482 MHz, AIN = –1 dBFS
fIN = 4997 MHz, AIN = –1 dBFS
fIN = 6397 MHz, AIN = –1 dBFS
fIN = 8197 MHz, AIN = –1 dBFS
53.0
51.6
50.0
57.4
57.6
57.4
57.3
57.4
57.0
52.7
52.4
48
52.1
47.5
46.6
47.7
8.6
8.5
7.7
8.4
7.7
7.5
7.6
dBFS
dBFS
dBFS
18
Submit Documentation Feedback
Product Folder Links: ADC12DJ3200
Copyright © 2017, Texas Instruments Incorporated