ADC12DJ3200 Datasheet, PDF (1/111 Pages) Texas Instruments – 6.4-GSPS Single Channel or 3.2-GSPS Dual Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)

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ADC12DJ3200
SLVSD97 – MAY 2017
ADC12DJ3200 6.4-GSPS Single Channel or 3.2-GSPS Dual Channel,
12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
1 Features
•1 ADC Core:
– 12-bit Resolution
– Up to 6.4 GSPS in single channel mode
– Up to 3.2 GSPS in dual channel mode
• Buffered Analog Inputs with V_CMI of 0 V
– Analog input bandwidth (-3 dB): 8.0 GHz
– Usable input frequency range: >10 GHz
– Full-scale input voltage (V_FS, default): 0.8 V_PP
• Noise Floor (No signal, V_FS = 1.0 V_PP):
– Dual channel mode: -151.8 dBFS/Hz
– Single channel mode: -154.6 dBFS/Hz
• Noiseless Aperture Delay (T_AD) Adjustment
– Precise sampling control: 19-fs step
– Temperature and voltage invariant delays
• Easy-to-use Synchronization Features
– Automatic SYSREF timing calibration
– Timestamp for sample marking
• JESD204B Serial Data Interface
– Supports subclass 0 and 1
– Maximum lane rate: 12.8 Gbps
– Up to 16 lanes allows reduced lane rate
• Digital Down-Converters in Dual Channel Mode
– Real output: DDC bypass or 2x decimation
– Complex output: 4x, 8x or 16x decimation
– Four independent 32-bit NCOs per DDC
• Power consumption: 3.0 W
• Power Supplies: 1.1 V, 1.9 V
3 Description
ADC12DJ3200 is an RF-sampling giga-sample ADC
that can directly sample input frequencies from DC to
above 10 GHz. In dual channel mode, ADC12DJ3200
can sample up to 3200-MSPS and in single channel
mode up to 6400-MSPS. Programmable tradeoffs in
channel count (dual channel mode) and Nyquist
bandwidth (single channel mode) allow development
of flexible hardware that meets the needs of both high
channel count or wide instantaneous signal
bandwidth applications. Full power input bandwidth (-
3 dB) of 8.0 GHz, with usable frequencies exceeding
the -3 dB point in both dual and single channel
modes, allows direct RF sampling of L-band, S-band,
C-band and X-band for frequency agile systems.
ADC12DJ3200 uses a high speed JESD204B output
interface with up to 16 serialized lanes and subclass-
1 compliance for deterministic latency and multi-
device synchronization. The serial output lanes
support up to 12.8 Gbps and can be configured to
trade-off bit rate and number of lanes. Innovative
synchronization features including noiseless aperture
delay (T_AD) adjustment and SYSREF windowing
simplify system design for phased array radar and
MIMO communications. Optional digital down
converters (DDCs) in dual channel mode allow for
reduction in interface rate (real and complex
decimation modes) and digital mixing of the signal
(complex decimation modes only).
Device Information⁽¹⁾
PART NUMBER
PACKAGE BODY SIZE (NOM)
ADC12DJ3200
FCBGA (144) 10.00 mm x 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Communications testers (802.11ad, 5G)
• Satellite communications (SATCOM)
• Phased array radar, SIGINT and ELINT
• Synthetic aperture radar (SAR)
• Time-of-flight and LIDAR distance measurement
• Oscilloscopes and wideband digitizers
• RF sampling software defined radio (SDR)
ADC12DJ3200 Measured Input Bandwidth
3
0
-3
-6
-9
Single Channel Mode
-12
Dual Channel Mode
-15
0
2
4
6
8
10
12
Input Frequency (GHz)
D_BW
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.