TM4C123FE6PM Datasheet, PDF (563/1370 Pages) Texas Instruments – Tiva™ TM4C123FE6PM Microcontroller

Tiva^™ TM4C123FE6PM Microcontroller
8.3.4
8.3.4.1
8.3.4.2
The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to
the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the
entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables
the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of
the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET)
register. This bit is automatically cleared when the transfer is complete. The status can also be
checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is
automatically cleared at the end of the transfer.
If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when
the entire transfer is complete.
Configuring a Peripheral for Ping-Pong Receive
This example configures the μDMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example
peripheral uses μDMA channel 8.
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
Configure the Channel Control Structure
This example transfers bytes from the peripheral's receive FIFO register into two memory buffers
of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use
the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used.
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the
alternate channel control structure is at offset 0x280. The channel control structures for channel 8
are located at the offsets shown in Table 8-11.
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Offset
Control Table Base + 0x080
Control Table Base + 0x084
Control Table Base + 0x088
Control Table Base + 0x280
Control Table Base + 0x284
Control Table Base + 0x288
Description
Channel 8 Primary Source End Pointer
Channel 8 Primary Destination End Pointer
Channel 8 Primary Control Word
Channel 8 Alternate Source End Pointer
Channel 8 Alternate Destination End Pointer
Channel 8 Alternate Control Word
June 12, 2014
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