ADS58C48_14 Datasheet, PDF (56/71 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

ADS58C48
SLAS689 – MAY 2010
www.ti.com
OFFSET CORRECTION
ADS58C48 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The
correction can be enabled using the serial register bit <EN OFFSET CORR>. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using register bits
<OFFSET CORR TIME CONSTANT> as described in Table 12.
After the offset is estimated, the correction can be frozen by setting <FREEZE OFFSET CORR > = 1. Once
frozen, the last estimated value is used for offset correction every clock cycle. Note that offset correction is
disabled by default after reset.
After a reset, the offset correction is disabled. To use offset correction:
• First, program the bits <DIGITAL MODE 1> and <DIGITAL MODE 2> as per the table above to enable the
correction.
• Then set <EN OFFSET CORR> to 1 and program the required time constant.
Table 12. Time Constant of Offset Correction Algorithm
OFFSET CORR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TIME CONSTANT (Number of clock
cycles)
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Reserved
Reserved
Reserved
Reserved
TIME CONSTANT, TC_CLK x
1/fs(sec) ⁽¹⁾
5.2 ms
10.5 ms
21 ms
42 ms
84 ms
167.8 ms
335.5 ms
671 ms
1.34 s
2.7 s
5.4 s
10.7 s
—
—
—
—
(1) Sampling frequency, Fs = 200 MSPS
56
Submit Documentation Feedback
Product Folder Link(s) :ADS58C48
Copyright © 2010, Texas Instruments Incorporated