ADS58C48_14 Datasheet, PDF (10/71 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

ADS58C48
SLAS689 – MAY 2010
INPUT
SIGNAL
Sample
N
N+1
N+2
N+3
N+4
t_a
INPUT
CLOCK
CLKP
CLKM
CLKOUTM
CLKOUTP
DDR
LVDS
OUTPUT DATA
CHx_P, CHx_M
10 clock cycles *
E O E O E O E O EOE
N-10
N-9
N-8
N-7
N-6
CLKOUT
PARALLEL
CMOS
OUTPUT DATA
10 clock cycles *
N-10
N-9
N-8
N-7
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N+11
N+10
N+12
t_SU
t_h
t_PDI
OE OE OE OE O
N
N+1
N+2
t_PDI
t_SU
t_h
N-1
N
1) ADC latency after reset, At higher sampling frequencies, t_PDI > 1 clock cycle which then makes the overall latency = ADC latency + 1.
2) E – Even bits D0, D2, D4…, O – Odd bits D1, D3, D5...
Figure 3. Latency Diagram
Input
Clock
Output
Clock
Output
Data Pair
CLKM
CLKP
CLKOUTM
CLKOUTP
CHx<>P/M
t_PDI
t_h
t_su
(1)
Dn
t_su
t_h
(2)
Dn+1
1. Dn - Bits D0,D2,D4...
2. Dn +1 - Bits D1,D3,D5...
Figure 4. LVDS Mode Timing
T0106-08
10
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