TM4C129CNCPDT Datasheet, PDF (552/1753 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this
register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both
corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt
controller.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
22
21
20
reserved
RO
RO
RO
RO
RO
0
0
0
0
0
8
7
6
5
4
VDDFAIL RSTWK PADIOWK WC
RO
RO
RO
RO
RO
0
0
0
0
0
19
18
17
16
RO
RO
RO
RO
0
0
0
0
3
2
1
0
EXTW LOWBAT reserved RTCALT0
RO
RO
RO
RO
0
0
0
0
Bit/Field
31:8
7
Name
reserved
VDDFAIL
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
VDD Fail Interrupt Mask
Value Description
0 An VDDFAIL interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a an arbitrary loss
of power or because on or more of the voltage supplies (VDD,
VDDA or VDDC) has dropped below the defined operating
range.
6
RSTWK
RO
0
Reset Pad I/O Wake-Up Interrupt Mask
Value Description
0 An external reset interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a RESET pin
assertion.
5
PADIOWK
RO
0
Pad I/O Wake-Up Interrupt Mask
Value Description
0 An external GPIO or reset interrupt has not occurred or is
masked.
1 An unmasked interrupt was signaled due to a wake-enabled
GPIO or RESET pin assertion.
552
June 18, 2014
Texas Instruments-Production Data