TM4C129CNCPDT Datasheet, PDF (1276/1753 Pages) Texas Instruments – Tiva Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
19.5
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Configure the UART clock source by writing to the UARTCC register.
6. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 664)
and enable the DMA option(s) in the UARTDMACTL register.
7. Enable the UART by setting the UARTEN bit in the UARTCTL register.
Register Map
Table 19-3 on page 1276 lists the UART registers. The offset listed is a hexadecimal increment to the
register's address, relative to that UART's base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
■ UART3: 0x4000.F000
■ UART4: 0x4001.0000
■ UART5: 0x4001.1000
■ UART6: 0x4001.2000
■ UART7: 0x4001.3000
The UART module clock must be enabled before the registers can be programmed (see page 385).
There must be a delay of 3 system clocks after the UART module clock is enabled before any UART
module registers are accessed.
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 1291) before any
of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation,
the current transaction is completed prior to the UART stopping.
Note: Registers that contain bits for modem control or status only apply to the following UARTs:
■ UART0 (modem flow control and modem status)
■ UART1 (modem flow control and modem status)
■ UART2 (modem flow control)
■ UART3 (modem flow control)
■ UART4 (modem flow control)
Table 19-3. UART Register Map
Offset Name
Type
0x000 UARTDR
RW
0x004 UARTRSR/UARTECR RW
0x018 UARTFR
RO
0x020 UARTILPR
RW
Reset
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
Description
UART Data
UART Receive Status/Error Clear
UART Flag
UART IrDA Low-Power Register
See
page
1278
1280
1283
1286
1276
Texas Instruments-Production Data
June 18, 2014