TM4C129CNCPDT Datasheet, PDF (1110/1753 Pages) Texas Instruments – Tiva Microcontroller

General-Purpose Timers
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTBILR determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this
value. Note that in edge-count mode, when executing an up-count, the value of GPTMTnPR and
GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM
signal.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the
current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the
match value. Bits 31:16 are reserved in both cases.
GPTM Timer B Match (GPTMTBMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x034
Type RW, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TBMR
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMR
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:0
Name
TBMR
Type
Reset Description
RW 0x0000.FFFF GPTM Timer B Match Register
This value is compared to the GPTMTBR register to determine match
events.
1110
Texas Instruments-Production Data
June 18, 2014