SRC4382_14 Datasheet, PDF (54/84 Pages) Texas Instruments – Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter

SRC4382
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
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This bit is used to mute the Port B audio data output.
BMUTE
Output Mute
0
Disabled; SDOUTB is driven by the output data source. (Default)
1
Enabled; SDOUTB is forced low.
Bit 7 (MSB)
0
BDIV[1:0]
BCLK[1:0]
Register 06: Port B Control Register 2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
0
0
0
BCLK1
BCLK0
BDIV1
BDIV0
Port B Master Mode Clock Divider
These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation.
BCKB is always set to 64 times the LRCKB clock rate in Master mode.
BDIV1
BDIV0
Master Mode Clock Divider
0
0
Divide By 128 (Default)
0
1
Divide By 256
1
0
Divide By 384
1
1
Divide By 512
Port B Master Clock Source
These bits are used to set the master clock source for Port B when configured for Master mode operation.
BCLK1
BCLK0
Master Clock Source
0
0
MCLK (Default)
0
1
RXCKI
1
0
RXCKO
1
1
Reserved
Bit 7 (MSB)
TXCLK
BSSL
VALID
BLSM
Bit 6
TXDIV1
Register 07: Transmitter Control Register 1
Bit 5
Bit 4
Bit 3
Bit 2
TXDIV0
TXIS1
TXIS0
BLSM
Bit 1
VALID
Bit 0 (LSB)
BSSL
Block Start or Asynchronous Data Slip Interrupt Trigger Selection
This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.
BSSL
TSLIP Interrupt Trigger Source
0
Data Slip Condition (Default)
1
Block Start Condition
Validity (V) Data Bit
This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for
V-bit source selection.
VALID
Transmitted Validity (V) Bit Data
0
Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital
processing. (Default)
1
Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further
digital processing.
Transmitter Block Start Input/Output Mode
This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35).
BLSM
BLS Pin Mode
0
Input (Default)
1
Output
54
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