TMS320C6748BZWT4 Datasheet, PDF (51/273 Pages) Texas Instruments – TMS320C6748 Fixed- and Floating-Point DSP

TMS320C6748
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SPRS590E – JUNE 2009 – REVISED AUGUST 2013
2.7.18 Ethernet Media Access Controller (EMAC)
Table 2-22. Ethernet Media Access Controller (EMAC) Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
PULL ⁽²⁾
POWER
GROUP ⁽³⁾
DESCRIPTION
MII
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6] C1
O
CP[5]
A
EMAC MII Transmit enable output
AXR5 / CLKX0 / GP1[13] / MII_TXCLK
D3
I
CP[5]
A
EMAC MII Transmit clock input
AXR4 / FSR0 / GP1[12] / MII_COL
D1
I
CP[5]
A
EMAC MII Collision detect input
AXR3 / FSX0 / GP1[11] / MII_TXD[3]
E3
O
CP[5]
A
AXR2 / DR0 / GP1[10] / MII_TXD[2]
AXR1 / DX0 / GP1[9] / MII_TXD[1]
E2
O
E1
O
CP[5]
CP[5]
A
A
EMAC MII transmit data
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] /
CLKS0
F3
O
CP[6]
A
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER
C16
I
CP[7]
A
EMAC MII receive error input
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS
C18
I
CP[7]
A
EMAC MII carrier sense input
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK
D19
I
CP[7]
A
EMAC MII receive clock input
SPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV
C17
I
CP[7]
A
EMAC MII receive data valid input
SPI0_SCS[5] /UART0_RXD / GP8[4] / MII_RXD[3]
C19
I
CP[8]
A
SPI0_SCS[4] /UART0_TXD / GP8[3] / MII_RXD[2]
D18
I
CP[8]
A
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /
SATA_MP_SWITCH
E17
I
CP[9]
A
EMAC MII receive data
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /
SATA_CP_DET
D16
I
CP[9]
A
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For electrical specifications on the pull-up and and internal pull-down circuits, see the Device Operating
Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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