DRV10983-Q1 Datasheet, PDF (51/72 Pages) Texas Instruments – Automotive, Three-Phase, Sensorless BLDC Motor Driver

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DRV10983-Q1
SLVSD14 – JUNE 2017
Table 24. EEPROM Programming3 Register Field Descriptions
Bit Field
15:8 Reserved
7:0 eeIndAddress[7:0]
Type
R
R
Reset
0x0
0x0
Description
Do not access these bits.
EEPROM individual access address.
Contents of this register define the address of EEPROM for the
individual access operation. For example, for writing/reading
CONFIG1 in individual access mode happens if eeIndAddress =
0x90.
8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]
Figure 57. EEPROM Programming4 Register
15
eeIndWData
[15]
R/W-0
14
eeIndWData
[14]
R/W-0
13
eeIndWData
[13]
R/W-0
12
eeIndWData
[12]
R/W-0
11
eeIndWData
[11]
R/W-0
10
eeIndWData
[10]
R/W-0
9
8
eeIndWData[9] eeIndWData[8]
R/W-0
R/W-0
7
eeIndWData[7]
R/W-0
6
eeIndWData[6]
R/W-0
5
eeIndWData[5]
R/W-0
4
eeIndWData[4]
R/W-0
3
eeIndWData[3]
R/W-0
2
eeIndWData[2]
R/W-0
1
eeIndWData[1]
R/W-0
0
eeIndWData[0]
R/W-0
Table 25. EEPROM Programming4 Register Field Descriptions
Bit Field
15:0 eeIndWData[15:0]
Type
R/W
Reset
0x00
Description
EEPROM individual access write data
Contents of this register are used to write to EEPROM data of
the registers specified by eeIndAddress.
8.5.3.17 EEPROM Programming5 Register (address = 0xYY) [reset = 0x00]
15
Reserved
R-0
7
Reserved
R-0
14
Reserved
R-0
6
Reserved
R-0
Figure 58. EEPROM Programming5 Register
13
Reserved
R-0
5
Reserved
R-0
12
ShadowRegEn
R/W-0
4
Reserved
R-0
11
Reserved
R-0
3
Reserved
R-0
10
Reserved
R-0
2
eeWRnEn
R/W-0
9
Reserved
R-0
1
eeAccMode[1]
R/W-0
8
R-0
0
eeAccMode[0]
R/W-0
Bit
15:13
12
11:9
8
7:3
2
Table 26. EEPROM Programming5 Register Field Descriptions
Field
Reserved
ShadowRegEn
Reserved
eeRefresh
Reserved
eeWRnEn
Type
R
R/W
Reset
000
0
R
000
R/W
0
R
0x0
R/W
0
Description
Do not access these bits.
Enable shadow register.
0 : Shadow register is not used.
1 : Shadow register values are used for device operation
(EEPROM contents are ignored). I²C read returns the contents
of the shadow registers.
Do not access these bits.
EEPROM refresh
0 : normal operation
1 : Sync shadow registers with contents of EEPROM.
Do not access these bits.
EEPROM refresh
0 : Normal operation
1 : Sync shadow registers with contents of EEPROM.
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