TMS320C28346_15 Datasheet, PDF (50/170 Pages) Texas Instruments – Delfino Microcontrollers

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
INT1
INT2
IFR(12:1)
INT11
INT12
(Flag)
IER(12:1)
(Enable)
INTM
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MUX
1
0
Global
Enable
CPU
INTx
MUX
PIEACKx
(Enable/Flag)
(Enable)
PIEIERx(8:1)
(Flag)
PIEIFRx(8:1)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
From
Peripherals
or
External
Interrupts
Table 3-8. PIE Peripheral Interrupts⁽¹⁾
CPU INTERRUPTS
INT1
INT2
INT3
INTx.8
WAKEINT
(LPM/WD)
EPWM8_TZINT
(ePWM8)
EPWM8_INT
(ePWM8)
INT4
Reserved
INT5
INT6
INT7
Reserved
SPITXINTD
(SPI-D)
Reserved
INT8
INT9
INT10
Reserved
ECAN1_INTB
(CAN-B)
Reserved
INT11
INT12
Reserved
LUF
(FPU)
INTx.7
TINT0
(TIMER 0)
EPWM7_TZINT
(ePWM7)
EPWM7_INT
(ePWM7)
Reserved
Reserved
SPIRXINTD
(SPI-D)
Reserved
Reserved
ECAN0_INTB
(CAN-B)
Reserved
Reserved
LVF
(FPU)
INTx.6
Reserved
EPWM6_TZINT
(ePWM6)
EPWM6_INT
(ePWM6)
ECAP6_INT
(eCAP6)
Reserved
MXINTA
(McBSP-A)
DINTCH6
(DMA)
SCITXINTC
(SCI-C)
ECAN1_INTA
(CAN-A)
Reserved
Reserved
Reserved
PIE INTERRUPTS
INTx.5
INTx.4
XINT2
XINT1
EPWM5_TZINT
(ePWM5)
EPWM5_INT
(ePWM5)
ECAP5_INT
(eCAP5)
EPWM4_TZINT
(ePWM4)
EPWM4_INT
(ePWM4)
ECAP4_INT
(eCAP4)
Reserved
Reserved
MRINTA
(McBSP-A)
DINTCH5
(DMA)
SCIRXINTC
(SCI-C)
ECAN0_INTA
(CAN-A)
MXINTB
(McBSP-B)
DINTCH4
(DMA)
Reserved
SCITXINTB
(SCI-B)
Reserved
Reserved
Reserved
Reserved
XINT7
XINT6
INTx.3
Reserved
EPWM3_TZINT
(ePWM3)
EPWM3_INT
(ePWM3)
ECAP3_INT
(eCAP3)
EQEP3_INT
(eQEP3)
MRINTB
(McBSP-B)
DINTCH3
(DMA)
Reserved
SCIRXINTB
(SCI-B)
Reserved
Reserved
XINT5
INTx.2
Reserved
EPWM2_TZINT
(ePWM2)
EPWM2_INT
(ePWM2)
ECAP2_INT
(eCAP2)
EQEP2_INT
(eQEP2)
SPITXINTA
(SPI-A)
DINTCH2
(DMA)
I2CINT2A
(I2C-A)
SCITXINTA
(SCI-A)
Reserved
Reserved
XINT4
INTx.1
Reserved
EPWM1_TZINT
(ePWM1)
EPWM1_INT
(ePWM1)
ECAP1_INT
(eCAP1)
EQEP1_INT
(eQEP1)
SPIRXINTA
(SPI-A)
DINTCH1
(DMA)
I2CINT1A
(I2C-A)
SCIRXINTA
(SCI-A)
EPWM9_TZINT
(ePWM9)
EPWM9_INT
(ePWM9)
XINT3
(1) Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there is one sage case when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
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Functional Overview
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