TMS320C28346_15 Datasheet, PDF (125/170 Pages) Texas Instruments – Delfino Microcontrollers

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.10.4 Low-Power Mode Wakeup Timing
The wakeup signal fed to a GPIO pin to wake up the device must meet the minimum pulse width
requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the
wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for
subsequent wakeup pulses.
Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and Figure 6-
11 shows the timing diagram for IDLE mode.
Table 6-13. IDLE Mode Timing Requirements⁽¹⁾
t_w(WAKE-INT)
Pulse duration, external wake-up
signal
Without input qualifier
With input qualifier
(1) For an explanation of the input qualifier parameters, see Table 6-12.
MIN
2t_c(SCO)
5t_c(SCO) + t_w(IQSW)
NOM
MAX
UNIT
cycles
Table 6-14. IDLE Mode Switching Characteristics⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
t_d(WAKE-IDLE)
Delay time, external wake signal to
program execution resume ⁽²⁾
• Wake-up from SARAM
Without input qualifier
With input qualifier
20t_c(SCO)
20t_c(SCO) + t_w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
Address/Data
(internal)
t_{d(WAKE−IDLE)}
XCLKOUT
WAKE INT^(A)
t_{w(WAKE−INT)}
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-11. IDLE Entry and Exit Timing
Copyright © 2009–2012, Texas Instruments Incorporated
Electrical Specifications 125
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