TMS320C28346_15 Datasheet, PDF (115/170 Pages) Texas Instruments – Delfino Microcontrollers

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
www.ti.com
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.7.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Table 6-4 through Table 6-5 list the cycle times of various clocks.
Table 6-4. Clocking and Nomenclature (300-MHz Devices)
MIN
NOM
MAX UNIT
On-chip oscillator clock (crystal/resonator–X1/X2)
t_c(OSC), Cycle time
Frequency
33.3
8
125 ns
30 MHz
XCLKIN ⁽¹⁾
PLL enabled
PLL disabled
t_c(CI), Cycle time (C8)
Frequency
t_c(CI), Cycle time (C8)
Frequency
6.67
2
6.67
4
50 ns
150 MHz
250 ns
150 MHz
X1 ⁽¹⁾
PLL enabled
t_c(CI), Cycle time (C8)
10
Frequency
2
PLL disabled
t_c(CI), Cycle time (C8)
10
Frequency
4
50 ns
100 MHz
250 ns
100 MHz
SYSCLKOUT
t_c(SCO), Cycle time
Frequency
3.33
2
500 ns
300 MHz
XCLKOUT
t_c(XCO), Cycle time
Frequency
13.3
0.5
2000 ns
75⁽²⁾ MHz
HSPCLK/EXTADCCLK ⁽³⁾
LSPCLK ⁽⁴⁾
t_c(HCO), Cycle time
Frequency
t_c(LCO), Cycle time
Frequency
25
6.67
13.3 ⁽⁵⁾
75 ⁽⁵⁾
ns
40 MHz
ns
150 MHz
(1) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
(2) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(3) This frequency is limited by GPIO switching characteristics.
(4) Lower LSPCLK and HSPCLK will reduce device power consumption.
(5) This is the value if SYSCLKOUT = 300 MHz.
Copyright © 2009–2012, Texas Instruments Incorporated
Electrical Specifications 115
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