SLAU443 Datasheet, PDF (50/68 Pages) Texas Instruments – EEG Front-End Performance Demonstration Kit

Bill of Materials, Layouts and Schematics
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9 Bill of Materials, Layouts and Schematics
This section contains the complete bill of materials, printed circuit board (PCB) layouts, and schematic
diagrams for the ADS1299EEG-FE.
NOTE: Board layouts are not to scale. These are intended to show how the board is laid out; do not
use for manufacturing ADS1299EEG-FE PCBs.
9.1 ADS1299EEG-FE Front-End Board Schematics
Figure 59 through Figure 63 shown the schematic diagrams of the ADS1299EEG-FE.
AVDD
AVDD
2
U11_3 3
AVSS
6
U11A
NI
R18
NI
U11_6
AVDD
2
6
U4_3 R17 3
NI
U4A
NI
AVSS
Optional 8-MSOP driver
R16 U4_6
NI
BIAS_SHD
BIAS_SHD
U2
4 ^NI
C21 NI
AGND
1
R4
NI
3
JP17
BIAS_DRV ^BIAS_DRV
C22 NI
AVSS
AGND
JP1
BIAS_ELEC
C20
0.01uF
R8
392K
R3 0
C23
1uF
AVDD
U1
ADS1299
AVDD
R1
NI
R5 NI
AVDD
R2
NI
AVSS
VCAP3
C3
1uF
C13
AVSS
0.1uF
DVDD
C76
C77
1uF
1uF
AVSS
AVDD
C6
C16
1uF
0.1uF
AVSS
AVDD
C4
C14
1uF
0.1uF
AVSS
AVDD
C7
C19
NI
NI
AGND
AVDD
C17
C18
1uF
0.1uF
AGND
JP6
U11_6 R15
0
BIAS_ELEC
BIAS_ELEC
REF_ELEC
REF_ELEC
C97 AVDD
1uF
AVDD
C8
C15
NI
NI
AVSS
2
JP7
U4_3 R13 3
0
C99
1uF AVSS
DVDD
C12
C5
0.1uF 1uF
AGND
6
U11
OPA376
R23
2M
2
3 U11_3
R24
2M
C24
1uF
AVSS
JP8
R25
6
R14
0
U4
OPA376
U4_6
0
C98
NI
TP1
TP2
TP11
AGND
AIN8N
AIN8P
AIN7N
AIN7P
AIN6N
AIN6P
AIN5N
AIN5P
AIN4N
AIN4P
AIN3N
AIN3P
AIN2N
AIN2P
AIN1N
AIN1P
VREFP
TP3
TP12
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
RESERVED
IN8N
IN8P
IN7N
IN7P
IN6N
IN6P
IN5N
IN5P
IN4N
IN4P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
RESV1
SRB1
SRB2
AGND
C10
10uF
AVSS
VREFP
C95
0.1uF
C1
1uF
AVSS
CLKSEL
DGND
DVDD
AVSS
DGND
DVDD
/DRDY
GPIO4
DOUT
GPIO2
GPIO3
SCLK
/CS
CLK
START
DIN
DGND
52
49
50
32
51
48
47
46
43
44
45
40
39
37
38
34
33
DVDD
R6
R7
10K
10K
CLKSEL
AGND
CLKSEL
SPI_DRDY
GPIO4
SPI_OUT
GPIO2
GPIO3
SPI_CLK
SPI_CS
SPI_DRDY
GPIO4
SPI_OUT
GPIO2
GPIO3
SPI_CLK
DVDD
R75
10K
SPI_CS
SPI_START
SPI_IN
SPI_START
SPI_IN
DVDD
JP19
C11
AGND
1uF
AGND
OSC1
4
VDD E/D
1
CLK
JP18
3
Output GND
2
HC735-2.048MHZ
/RESET
GPIO1
/PWDN
DAISY_IN
/RESET
GPIO1
/PWDN
DAISY_IN
EXT_CLK
EXT_CLK
JP5
C33
C9
C2
AGND
NI
100uF
1uF
AVSS
AVSS
GPIO4
GPIO3
J5
21
43
65
87
10 9
NI
/PWDN
DAISY_IN
AGND
Figure 59. ADS1299EEG-FC Schematic
AGND
50
EEG Front-End Performance Demonstration Kit
Copyright © 2012, Texas Instruments Incorporated
SLAU443 – May 2012
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