SLAU443 Datasheet, PDF (16/68 Pages) Texas Instruments – EEG Front-End Performance Demonstration Kit

ADS1299EEG-FE Daughter Card Hardware Introduction
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A 2.048MHz oscillator available for +3V and +1.8V DVDD is the FXO-HC735-2.048MHz and SiT8002AC-
34-18E-2.048, respectively. The EVM is shipped with the external oscillator enabled.
4.3 Reference
The ADS1299 has an on-chip internal reference circuit that provides reference voltages to the device.
Alternatively, the internal reference can be powered down and VREFP can be applied externally. This
configuration is achieved with the external reference generator (U3) and driver buffer. The EVM has the
footprints for the necessary circuitry, but the components are not installed at the factory.
The external reference voltage can be set to 4.096V. Measure TP3 to make sure the external reference is
correct. The setting for the external reference is described in Table 6.
Table 6. External Reference Jumper Options
ADS1299 Reference
JP3
Internal Reference
VREF = 4.5V
Not Installed
External Reference
VREFP = 4.096V
Installed
The software uses the VREF value entered in the Global Registers control tab (refer to Section 5.2) to
calculate the input-referred voltage value for all the tests. The default value is 4.5V. If any other value is
used, the user must update this field in the Global Registers control tab.
4.4 Accessing ADS1299 Analog Signals
Some ADS1299 output signals are provided as test points for probing purposes through J5. Table 7 lists
the various test signals with the corresponding test points.
Signal
RESERVE
RESERVE
GPIO4
GPIO3
AGND
Table 7. Test Signals
J5 Pin Number
1
2
3
4
5
6
7
8
9
10
Signal
RESERVE
RESERVE
PWDNB
Daisy_in
RESERVE
4.5 Accessing ADS1299 Digital Signals
The ADS1299 digital signals (including SPI interface signals, some GPIO signals, and some of the control
signals) are available at connector J3. These signals are used to interface to the MMB0 board DSP. The
pin out for this connector is given in Table 8.
Signal
START/CS
CLK
NC
CS
NC
DIN
DOUT
DRDYB
EXT_CLK
NC
Table 8. Serial Interface Pin Out
J3 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal
CLKSEL
GND
GPIO1
RESETB
GND
GPIO2
NC/START
SCL
GND
SDA
16
EEG Front-End Performance Demonstration Kit
Copyright © 2012, Texas Instruments Incorporated
SLAU443 – May 2012
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