PCI1210GGU Datasheet, PDF (50/128 Pages) Texas Instruments – PCI1210 GGU/PGE PC CARD CONTROLLERS

PCI1210 GGU/PGE
PC CARD CONTROLLERS
SCPS032A– APRIL 1998
secondary status register
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Secondary status
Type
R/C R/C R/C R/C R/C R
R R/C R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register: Secondary status
Type:
Read only, read/clear (see individual bit descriptions)
Offset:
16h
Default: 0200h
Description: The secondary status register is compatible with the PCI-to-PCI bridge secondary status
register, and indicates CardBus-related device information to the host system. This register is
very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1.
See Table 19 for the complete description of the register contents.
BIT
15
14
13
12
11
10–9
8
7
6
5
4–0
SIGNAL
CBPARITY
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
CB_DPAR
CBFBB_CAP
CB_UDF
CB66MHZ
RSVD
TYPE
R/C
R/C
R/C
R/C
R/C
R
R/C
R
R
R
R
Table 19. Secondary Status Register
FUNCTION
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1210 does not
assert CSERR.
Received master abort. Bit 13 is set when a cycle initiated by the PCI1210 on the CardBus bus has been
terminated by a master abort.
Received target abort. Bit 12 is set when a cycle initiated by the PCI1210 on the CardBus bus is
terminated by a target abort.
Signaled target abort. Bit 11 is set by the PCI1210 when it terminates a transaction on the CardBus bus
with a target abort.
CDEVSEL timing. These read-only bits encode the timing of CDEVSEL and are hardwired 01b,
indicating that the PCI1210 asserts CB_SPEED at a medium speed.
CardBus data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The PCI1210 was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control.
Fast back-to-back capable. The PCI1210 cannot accept fast back-to-back transactions; thus, bit 7 is
hardwired to 0.
User-definable feature support. The PCI1210 does not support the user-definable features; thus, bit 6
is hardwired to 0.
66-MHz capable. The PCI1210 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
Reserved. Bits 4–0 return 0s when read.
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