PCI1210GGU Datasheet, PDF (37/128 Pages) Texas Instruments – PCI1210 GGU/PGE PC CARD CONTROLLERS

PCI1210 GGU/PGE
PC CARD CONTROLLERS
SCPS032A– APRIL 1998
using parallel IRQ interrupts (continued)
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10,
IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This
value routes the MFUNC0 terminal to INTA signaling, and routes the remaining terminals as illustrated in
Figure 15. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some
circuitry that provides parallel PCI interrupts to the host.
PCI1210
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PIC
IRQ3
IRQ4
IRQ5
IRQ10
IRQ11
IRQ15
Figure 15. Example of IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ
configuration of a system implementing the PCI1210. Refer to the multifunction routing register description on
page 61 for details on configuring the multifunction terminals.
The parallel ISA type IRQ signaling from the MFUNC6:0 terminals is compatible with those input directly into
the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. There may
be design constraints that demand more MFUNC6:0 IRQ terminals than the PCI1210 makes available. A
system designer may choose to implement an IRQSER deserializer companion chip, such as the Texas
Instruments PCI950. To use a deserializer, the MFUNC3 terminal must be configured as IRQSER and
connected to the deserializer, which outputs all 15 ISA IRQ’s and four PCI interrupts as decoded from the
IRQSER stream.
using parallel PCI interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling
mode, and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed
to INTA (MFUNC0).
using serialized IRQSER interrupts
The serialized interrupt protocol implemented in the PCI1210 uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet
data describes sixteen parallel ISA IRQ signals and the optional four PCI interrupts INTA, INTB, INTC, and
INTD. For details on the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems.
SMI support in the PCI1210
The PCI1210 provides a mechanism of interrupting the system when power changes have been made to the
PC Card socket interface. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. When enabled, SMI interrupts are generated by the PCI1210 after a write cycle to either the CardBus
socket control register or the ExCA power control register.
The SMI control is programmed through three bits in the system control register. These bits are SMIROUTE,
SMISTATUS, and SMIENB. The SMI control bits function as described in Table 14.
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