BQ2060SS Datasheet, PDF (50/59 Pages) Texas Instruments – SBS V1.1-COMPLIANT GAS GAUGE IC

bq2060
SLUS035E – JANUARY 2000 – REVISED OCTOBER 2005
SM
The SM bit enables/disables master mode broadcasts by the bq2060
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0
Broadcasts to host and charger enabled
1
Broadcasts to host and charger disabled
If the SM bit is set, modifications to bits in BatteryMode() does not re-enable broadcasts.
MEASUREMENT CALIBRATION
ADC
To describe how the bq2060 calculates reported battery and individual cell voltages, the following abbreviations
and designations are used:
VCELL₁–4 = voltages at the input pins of the bq2060
VCELL1–4 = reported cell voltages
Vnl–4 = voltages at the different series nodes in the battery
Voltage() = reported battery voltage
V_sr = voltage across the sense resistor
The reported voltages measurements, Voltage() and VCELL1–4, may be calibrated by adjusting five 8- or 16-bit
registers in EEPROM: ADC Offset in EE0x62, ADC Voltage Gain in EE 0x66–0x67, Cell 2 Calibration Factor in
EE 0x63, Cell 3 Calibration Factor in EE 0x64, and Cell 4 Calibration Factor in EE 0x65.
The bq2060 first computes the node voltages Vnl, Vn2, Vn3, and Vn4. The node voltages are inputs to the volt-
age dividers to the VCELL₁through VCELL₄ input pins of the bq2060. The bq2060 computes node voltages to
calculate the five reported voltages by the bq2060: Voltage(), VCELL1, VCELL2, VCELL3, and VCELL4.
An ADC Voltage Gain factor of 20,000 is the nominal value when using the recommended cell-voltage division
ratios of 16:1 on the VCELL₄ and VCELL₃ inputs and 8:1 on the VCELL₂ and VCELL₁ inputs. The bq2060
subtracts the voltage across the sense resistor from the measurements so that the reported voltages reflect the
cell-stack voltages only.
The bq2060 compute the node voltages as
ƪ ƫ ƪ ƫ Vn1 +
VCELL 32768
1250
)
ADC
Offset
ADC Voltage Gain
65536
(27)
ƪ ƫ _{ƪ ƫ} Vn2 +
VCELL 32768
1250
)
ADC
Offset
ADC Voltage Gain ) 8 (Cell 2 CalibrationFactor)
65536
(28)
ƪ ƫ Vn3 +
VCELL 32768
1250
)
ADC
Offset
ƪ ƫ ƪADC Voltage Gain ) 8 (Cell 3 CalibrationFactor)ƫ
2
65536
(29)
ƪ ƫ Vn4 +
VCELL 32768
1250
)
ADC
Offset
ƪ ƫ ƪ_{ADC Voltage Gain ) 8 (Cell 4 CalibrationFactor)}ƫ
2
65536
(30)
Note: With LCC1-LCC0 = 00, Cell 4 Calibration Factor = 0.
ADC Offset adjusts the ADC reading for voltage and current measurements. ADC Offset is a signed 8-bit value
that cancels offset present in the circuit with no potential or current flow. ADC Offset is typically set between -20
and 20.
50