BQ2060SS Datasheet, PDF (17/59 Pages) Texas Instruments – SBS V1.1-COMPLIANT GAS GAUGE IC

bq2060
www.ti.com
CONDITION
RELATIVE OR
ABSOLUTE
STATEOFCHARGE()
EDV0 = 1
<25%
≥25%, <50%
≥50%, <75%
≥75%
SLUS035E – JANUARY 2000 – REVISED OCTOBER 2005
Table 8. DISPLAY MODE (4 LED)
4 LED DISPLAY OPTION
LED1
LED2
LED3
LED4
OFF
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
Communication
The bq2060 includes two types of communication ports: SMBus and HDQ16. The SMBus interface is a 2-wire
bidirectional protocol using the SMBC (clock) and SMBD (data) pins. The HDQ16 interface is a 1-wire
bidirectional protocol using the HDQ16 pin. All three communication lines are isolated from V_CC and may be
pulled up higher than V_CC. Also, the bq2060 does not pull these lines low if V_CC to the part is zero. HDQ16
should be pulled down with a 100-kΩ resistor if not used.
The communication ports allow a host controller, an SMBus-compatible device, or other processor to access the
memory registers of the bq2060. In this way a system can efficiently monitor and manage the battery.
SMBus
The SMBus interface is a command-based protocol processor acting as the bus master initiates communication
to the bq2060 by generating a START condition. The START condition consists of a high-to-low transition of the
SMBD line while the SMBC is high. The processor then sends the bq2060 device address of 0001011 (bits 7–1)
plus a R/W bit (bit 0) followed by an SMBus command code. The R/W bit and the command code instruct the
bq2060 to either store the forthcoming data to a register specified by the SMBus command code or output the
data from the specified register. The processor completes the access with a STOP condition. A STOP condition
consists of a low-to-high transition of the SMBD line while the SMBC is high. With the SMBus protocol, the most
significant bit of a data byte is transmitted first.
In some instances, the bq2060 acts as the bus master. This occurs when the bq2060 broadcasts charging
requirements and alarm conditions to device addresses 0x12 (SBS Smart Charger) and 0x10 (SBS Host
Controller.)
SMBus Protocol
The bq2060 supports the following SMBus protocols:
• Read Word
• Write Word
• Read Block
A processor acting as the bus master uses the three protocols to communicate with the bq2060. The bq2060
acting as the bus master uses the WriteWord protocol.
The SMBD and SMBC pins are open drain and require external pullup resistors.
SMBus Packet Error Checking
The bq2060 supports Packet Error Checking as a mechanism to confirm proper communication between it and
another SMBus device. Packet Error Checking requires that both the transmitter and receiver calculate a Packet
Error Code (PEC) for each communication message. The device that supplies the last byte in the communication
message appends the PEC to the message. The receiver compares the transmitted PEC to its PEC result to
determine if there is a communication error.
PEC Protocol
The bq2060 can receive or transmit data with or without PEC. Figure 8 shows the communication protocol for the
Read Word, Write Word, and Read Block messages without PEC. Figure 9 includes PEC.
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