TLC5617_05 Datasheet, PDF (5/21 Pages) Texas Instruments – PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref (REFIN)= 2.048 V (unless otherwise noted) (continued)
digital inputs (DIN, SCLK, CS)
PARAMETER
IIH High-level digital input current
IIL
Low-level digital input current
Ci
Input capacitance
TEST CONDITIONS MIN
VI = VDD
VI = 0 V
TYP MAX UNIT
± 1 µA
± 1 µA
8
pF
power supply
PARAMETER
Supply voltage, VDD
IDD Power supply current
Power down supply current
TEST CONDITIONS
VDD = 5.5 V,
No load,
All inputs = 0 V or VDD
D13 = 0 (see Table 3)
Slow
Fast
MIN TYP MAX UNIT
4.5
5 5.5 V
0.6
1
mA
1.6 2.5
1
µA
operating characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SR
Output slew rate
CL = 100 pF,
RL = 10 kΩ,
Code 32 to Code 1024,
Vref(REFIN) = 2.048 V,
TA = 25°C,
VO from 10% to 90%
Slow 0.3 0.5
Fast
2.4
3
V/µs
ts
Output settling time
To ± 0.5 LSB,
RL = 10 kΩ,
CL = 100 pF,
See Note 10
Slow
12.5
µs
Fast
2.5
ts(c)
Output settling time, code To ± 0.5 LSB,
to code
RL = 10 kΩ,
CL = 100 pF,
See Note 11
Slow
Fast
2
µs
2
S/(N+D)
Glitch energy
Signal to noise + distortion
DIN = All 0s to all 1s,
f(SCLK) = 100 kHz
CS = VDD,
Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000
Slow
Fast
5
nV–s
78
dB
81
NOTES: 10. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Setting time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.
digital input timing requirements
tsu(DS)
th(DH)
tsu(CSS)
tsu(CS1)
tsu(CS2)
tw(CL)
tw(CH)
Setup time, DIN before SCLK low
Hold time, DIN valid after SCLK low
Setup time, CS low to SCLK low
Setup time, SCLK ↑ to CS ↑, external end-of-write
Setup time, SCLK ↑ to CS ↓, start of next write cycle
Pulse duration, SCLK low
Pulse duration, SCLK high
MIN NOM MAX UNIT
5
ns
5
ns
5
ns
10
ns
5
ns
25
ns
25
ns
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5