TLC5617_05 Datasheet, PDF (13/21 Pages) Texas Instruments – PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
APPLICATION INFORMATION
SLAS151B – JULY 1997 – REVISED MARCH 2000
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. All CS transitions should occur when the SCLK
input is low.
The 16 bits of data can be transferred with the sequence shown in Figure 18.
Program Bits
16 Bits
Data Bits
Fill Bits†
D15
D14
D13
D12
D11
10 Data Bits
D2 D1 = x D0 = x
MSB (Input Word)
MSB (Data)
† _{Two extra (sub-LSB) bits (can be don’t care)}
LSB (Data)
LSB (Input Word)
Figure 18. Input Data Word Format
Table 2 shows the function of program bits D15 – D12.
Table 2. Program Bits D15 – D12 Function
PROGRAM BIT
D15
D14
D13
D12
DEVICE FUNCTION
1
X
X
X
Write to latch A with serial interface register data
and latch B updated with buffer latch data
0
X
X
0 Write to latch B and double buffer latch
0
X
X
1 Write to double buffer latch only
X
1
X
X 12.5 µs settling time
X
0
X
X 2.5 µs settling time
X
X
0
X Powered-up operation
X
X
1
X Powered-down mode
function of the latch control bits (D15 and D12)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.
latch A write, latch B update (D15 = high, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This control bit condition allows simultaneous output updates
of both DACs.
Serial
Interface
Register
Latch A
To DAC A
D12 = X
D15 = High
Double
Buffer
Latch
Latch B
To DAC B
Figure 19. Latch A Write, Latch B Update
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